Electronic devices, for example field effect transistors (FETs) are used in display devices and logic capable circuits. A conventional FET typically includes source, drain and gate electrodes, a semiconducting layer made of a semiconductor (SC) material, and an insulator layer (also referred to as “dielectric” or “gate dielectric”), made of a dielectric material and positioned between the SC layer and the gate electrode. Also known are organic electronic devices, for example organic field effect transistors (OFETs) that are useful in display devices and logic capable circuits. A conventional OFET also includes source, drain and gate electrodes but rather than an inorganic semiconductor layer, an OFET includes a semiconducting layer made of an organic semiconductor (OSC) material and generally an insulator layer made of an organic dielectric material positioned between the OSC layer and the gate electrode.
U.S. Pat. No. 7,029,945 B2 discloses embodiments of an organic field effect transistor (OFET) wherein the gate insulator layer is made of a dielectric material having a permittivity (∈) (also known as relative permittivity or dielectric constant (k)) of less than 3.0. Such materials, generally referred as “low k materials”, are reported to provide good mobility regardless of whether or not the organic semiconductor layer is disordered or semi-ordered. US '945 further reports that commercially available fluoropolymers such as Cytop™ (from Asahi Glass) or Teflon AF™ (from DuPont) are exemplary low k materials.
In EP1687830B1 the use of Cytop as a gate insulator material is disclosed as being advantageous for solution processed OFET devices where the OSC material is selected from soluble, substituted oligoacenes, such as pentacene, tetracene, anthracene, or heterocyclic derivatives thereof. These OSC materials are soluble in most common organic solvents. Therefore, when preparing a top gate OFET, the solvents for the gate dielectric formulation have to be carefully chosen to avoid dissolution of the OSC material by the solvent of the gate dielectric formulation when deposited in adjacent layers. Such a solvent is generally referred to as being orthogonal to the material of the OSC layer. Similarly, when preparing a bottom gate device, the solvent for carrying the OSC material onto a previously formed gate dielectric layer is selected to be orthogonal to the gate dielectric material.
It has been reported that the above-mentioned fluoropolymers are problematic with regard to limited structural integrity and integration into processing in the mass production of OFET devices. Regarding proccessability, fluoropolymers often do not adhere well to other layers, for example the substrate and OSC layer, among others, generally exhibiting poor wetting of such layers. Also, many fluoropolymers, such as those of the aforementioned Cytop™ series, have low glass transition temperatures, Tg (˜100-130° C.) that make it difficult to use standard physical or chemical deposition methods for applying a metallized gate electrode layer over such a fluoropolymer dielectric layer. With regard to structural integrity, if a fluoropolymer having a low Tg is heated to, or above the Tg temperature during a metallization process, polymer cracking due to built-in stress can occur. Even where such cracking can be avoided, differential expansion between the fluoropolymer and any adjacent layer due to heating can result in polymer wrinkling. Where fluoropolymers with a higher Tg, like those of the Teflon AF™ series (e.g., Teflon AF 2400 with Tg=240° C.), have been used to overcome the aforementioned wrinkling or cracking problems, such materials often exhibit wetting and adhesion problems that are more severe than those exhibited by the low Tg materials. Thus there is a need for a polymer with good wettability and high Tg capable of forming a low k gate dielectric layer.
In FIGS. 3 to 22, the X-axis depicts the gate voltage, left Y-axis depicts the drain current, and the right Y-axis depicts the mobility. The upper two curves, which are exemplarily labeled “c” in FIG. 3, depict the current-voltage characteristic for forward and reverse scans, illustrating the current hysteresis of the device. The lower two curves, which are labeled “a” and “b” as exemplarily shown in FIG. 3, depict the mobility-voltage characteristic, wherein curve (a) shows the mobility obtained in the linear regime, and curve (b) shows the mobility obtained in the saturation mode.